In the packaging of semiconductor chips, a hierarchy of interconnections is necessary. At the level of the interconnection between the chip and the substrate (or chip carrier), three different interconnection technologies are widely employed: tape automated bonding (TAB), wire bonding, and area array flip chip interconnect.
The solder bump area array interconnect scheme is often called flip-chip solder connection or C4, the face-down soldering of integrated circuit devices (IC) to chip carriers. Unlike wirebonding, the area array solder bump configuration allows the entire surface of the chip to be covered with C4 bumps for the highest possible input/output (I/O) counts to meet the ever increasing demand on the electrical functionality and reliability of the IC technology, than can wire bonding or TAB, which confine the interconnections to the chip periphery.
More specifically, the C4 technology uses solder bumps deposited on a patterned solder-wettable layered structure known as the ball-limiting metallurgy (BLM), which is also called under-bump metallurgy (UBM). Ball-limiting metallurgy (hereinafter the “BLM”) defines the terminal metal pads on the top surface of the front- and back-end-of-line (FEOL and BEOL) wiring layers fabricated on the chip that is wettable by the solder, and which also limits the lateral flow of molten solder away from the terminal pad area. After the solder bumps are fabricated on the patterned UBM pads on the chip to form balls, the chips are joined to a matching footprint of solder-wettable pads on the chip carrier. It is the face-down placement of the chip on the carrier that has led C4 technology to be called flip-chip joining. Compared to other methods of interconnection, the C4 technology offers distinct advantages, including the following: 1) shorter interconnect distances, allowing faster signal response and reduced inductance coupling and cross-talk; 2) more uniform power and heat distribution; 3) reduced simultaneous switching noise; and 4) greater design flexibility with the highest possible total input/output counts.
Fabrication of Pb—Sn C4 interconnections by evaporation through a metal mask has been developed and perfected since the mid-1960s by IBM. Both the C4 bumps and BLM pads are evaporated through the patterned metal masks to form a highly reliable, high-density interconnect structure; it has proven extendability from the earliest low density, low Input/output counts smaller IC devices through the high density, high input/output count IC products of the 2000s. However, it is believed that the limit of extendibility to larger wafer sizes, more dense arrays and Pb-free applications has nearly been reached by the evaporation method.
Alternative methods to evaporation are electro-plating, paste screening, solder jetting and, more recently, the C4NP, which stands for C4 “New Process”, to name a few. Electrochemical plating fabrication of C4s, which is a selective and efficient process, has been reported in the literature by, for example, Yung in U.S. Pat. No. 5,162,257, which is incorporated herein by reference. Manufacturability and other integration issues of electrochemically fabricated C4s have been described by Datta, et al. in the J. Electrochem. Soc., 142, 3779 (1995), which is also incorporated herein by reference. Using plating and etching processes, and through the development of sophisticated tools, it is possible to obtain a high degree of compositional and volume uniformity of electroplated solders, uniform dimensions of the ball-limiting metallurgy (BLM), and a controlled BLM edge profile.
The electrochemical process is more extendible to larger wafers and to finer C4 dimensions than the evaporated C4 technology. Electrodeposition through a photoresist mask produces solder only in the mask opening and on top of the UBM. Electrodeposition, in contrast to evaporation, is extendible to high-tin content lead-free alloys and large 300 mm wafers.
The C4NP fabricated C4 solder bumps have been described in the literature by Gruber, et al. in U.S. Pat. No. 6,231,333, which is incorporated herein by reference. Manufacturing and other integration issues of C4NP fabricated C4s have also been described by Gruber, et al. in the IBM J. RES & DEV. 49, 4/5 (2005), which is incorporated herein by reference. The technology makes efficient use of bulk solders that easily incorporate multi-component ternary and quaternary leaded and no-lead solder alloys, with precisely controlled solder composition and low alpha particle control to perform environmental-friendly wafer bumping to achieve both high density and low cost applications. It can achieve high degrees of dimensional and volume uniformity, and is extendible to large 300 mm wafers.
A generic C4 structure consists of all of the elements beginning with the ball-limiting metallurgy (hereinafter the “BLM”). The multi-layer BLM structure generally consists of an adhesion layer, a reaction barrier layer, and a wettable layer to facilitate solder bump joining between the IC device and the interconnection structure, the chip carriers. The different metal layers in the BLM structure are chosen to be compatible with each other and with the solder alloys, to meet not only stringent electrical, mechanical and reliability requirements in the C4 joint, but also to allow easy fabrication.
A detailed description of the elements comprising a three-layer BLM structure and C4 bumps are summarized as follows.
1) The first layer to be deposited on the top surface of wafer is the adhesion layer of the BLM which provides adhesion to the underlying substrate. This layer can also serve as a diffusion/reaction barrier layer to prevent any interaction between the back-end-of-line (BEOL) wiring layers with solder. This is a thin layer typically deposited by sputtering, evaporation or induction heating on the surface of the wafer passivation layer, which is commonly made of polymer, oxide or nitride materials, or the combination of them. Candidates for adhesion layer are Cr, Ti, W, TiW, Ta, TiN, TaN, Zr etc. to name a few, on the order of hundreds to thousands angstroms in thickness.
2) The next layer of the BLM is a reaction barrier layer which is solderable by the molten solder but react slowly (limited controlled reaction) to allow for multiple thermal ref low cycles (or rework cycles) without being totally consumed. Candidates for a reaction barrier layer are Ni, Co, W, Ru, Hf, Nb, Mo, V, Ta and their alloys, to name a few. This layer is typically on the order of thousands of angstroms to microns in thickness, deposited by sputtering, evaporation, electroless- or electrolytic plating.
3) The final layer of the BLM is the wettable layer, allowing easy solder wettability and fast reaction with solder. Typical examples are copper, palladium, gold, tin and their alloys, typically in the range of a few hundreds to thousands of angstroms in thickness, deposited by sputtering, evaporation, electroless- or electrolytic plating. In some special chip joining applications, Cu thickness can be increased to the range of microns in thickness.
4) For the C4 bumps formed on top of the BLM structure, a number of manufacturing processes have been developed that include evaporation, plating, stencil printing, paste screening and solder jetting, and molten solder injection, to name a few.
5) After formation of the bumps, solder bumps are reflowed. Reflow is done typically in an inert or reducing atmosphere (N2 or H2/N2 mixture gas) in a belt furnace or in a vacuum furnace or in an oven. During reflow, intermetallic compounds form between solder and the reaction barrier layer. These compounds serve to provide good mechanical integrity for a reliable solder joint.
6) Finally, the wafer is tested and diced into chips, through a dice, sort and pick (DSP) operation. Good chips (those passed electrical test specifications) are picked and are aligned and flip joined to a chip carrier through the use of a suitable flux or fluxless joining.